In the rapidly evolving semiconductor manufacturing sector, the quest for higher yields and cost efficiencies presents significant challenges. Industry experts assert that yield should ideally only decrease due to unavoidable defects, and process sensitivity in design can be addressed when necessary. However, advancing technology has opened up new avenues for mitigating yield loss, particularly through emerging artificial intelligence solutions.
One such innovation comes from proteanTecs, which has developed a cloud-based application designed to monitor and correlate failing production test bins using deep data gathering agents. The application integrates with an edge solution, allowing for real-time decision-making during automated test equipment (ATE) testing. When correlations between failing pins are detected, alerts are sent to customers, facilitating prompt corrective action. “While improving the design process sensitivity is the preferable solution,” a representative from proteanTecs mentioned, “in some cases, addressing these issues directly within the design is either not feasible or overly complex.”
To counteract issues associated with yield loss, the application advocates for a “shift-left” approach—essentially identifying and disqualifying problematic chips at the earliest stages of production testing, specifically during the wafer sort process. This preventative measure aims to reduce costs by minimising the number of chips that fail later in the process, particularly at the costly packaged device testing phase. Notably, with semiconductor packages becoming increasingly intricate, such as 2.5D and 3D heterogeneous packages, the economic advantages of early disqualification become all the more pronounced.
Traditional semiconductor manufacturing practices have heavily relied on final testing to ensure chip quality, which can lead to wasted resources, given that chips that ultimately fail have often undergone extensive packaging and related processes. By shifting the detection of potential failures upstream, specifically to the wafer sort stage, proteanTecs’s solution proposes an evolution in how manufacturers approach yield management.
The predictive capabilities of the proteanTecs tool enable manufacturers to identify "soft (failing) bins," or sub-categories of test results, before additional resources are allocated. According to proteanTecs, understanding which chips are likely to fall into specific failing bins offers considerable advantages for manufacturers, allowing for more informed decisions regarding packaging and subsequent testing processes. The need for early detection has garnered particular importance in light of escalating costs associated with packaging, test programme development, and system-level testing.
Utilising machine learning algorithms, the proteanTecs platform is trained using the data gleaned from on-chip monitoring during the wafer sort process. This deep data analysis allows for accurate predictions about which chips may fail during later testing phases. The training occurs within the proteanTecs cloud infrastructure, from which optimized models can be seamlessly integrated into testers via their edge library.
Moreover, the model's ability to provide insights into feature importance—a metric that indicates which parameters significantly influence testing outcomes—enables manufacturers to modify variables for improved yield. By identifying design sensitivities that could lead to higher failure rates, firms have the opportunity to take preemptive measures during the design phase, potentially leading to a more robust manufacturing process.
A case study related to the testing of a 5nm data centre compute chip illustrates the shift-left application’s predictive capabilities. The Receiver Operating Characteristic (ROC) curves demonstrated in the analysis reveal high accuracy in predicting specific soft bins, with area under the curve (AUC) values of 0.94 and 0.935. Data indicated that the predictive model successfully identified 50% of chips that would later fall into a failing bin during the wafer sort phase, marking a step forward in proactive decision-making during production.
The developments facilitated by proteanTecs signify a paradigm shift in semiconductor manufacturing practices. By adopting smarter, data-driven decision strategies through on-chip monitoring and machine learning, manufacturers can look forward to improvements in yield optimisation, significant cost reductions, and an overall more efficient production process. As the semiconductor landscape continues to advance, the capability to preemptively address potential failures is poised to become increasingly essential for companies striving to maintain their competitive edge.
Source: Noah Wire Services