The semiconductor industry is undergoing significant advancements in the fabrication of through-silicon vias (TSVs) as demand increases for various applications including high-bandwidth memory (HBM), integrated radio frequency (RF), power components, and microelectromechanical systems (MEMS). This trend is propelled by the growing need for 3D packaging solutions that enable smaller and more efficient devices in mobile, augmented reality (AR), virtual reality (VR), biomedical, and wearable sectors.
TSVs provide a critical means of enhancing connectivity between integrated circuits by enabling shorter interconnect lengths, which in turn lowers power consumption and reduces latency. Notable advancements are being made in TSV technology, allowing for the development of thinner and more compact modules. Notably, TSVs are employed in HBM to facilitate faster data transfer at reduced power levels compared to traditional DDR5 memory. The industry is currently evaluating TSV sizes, with applications ranging from a few micrometres in CMOS image sensors to sub-5nm for advanced power delivery.
Despite the longstanding history of TSV technology, challenges remain, particularly around cost-efficiency and fabrication processes. As TSVs become smaller and their aspect ratios increase, fabrication costs also rise due to the more complex processes needed to create deeper trenches and manage the integration of various materials. Consequently, equipment and materials suppliers are focusing on ensuring reliability while driving down costs associated with TSV fabrication.
Marc Swinnen, director of product marketing at Ansys, highlighted the mechanical and thermal stresses that TSVs exert on surrounding silicon. He noted that while ideally, TSVs would be distributed uniformly to evenly distribute warping stresses, practical connectivity requirements often lead to non-uniform placements, resulting in clusters and voids that can affect overall performance.
Research conducted by Masaki Haneda and colleagues at Sony explored the proximity effects of closely spaced TSVs, which may influence long-term reliability. Experiments were carried out with specific experimental setups to ensure high reliability amidst these stresses, linking the density of TSV layouts to device placement efficiency.
The fabrication of TSVs comprises multiple intricate steps, beginning with lithography and reactive ion etching and culminating in copper electroplating and chemical-mechanical planarization. Each stage is crucial, as defects can arise from any of the actions taken throughout the process. Chee-Ping Lee, technical director at Lam Research, drew attention to the challenges of achieving reliably filled TSVs, stating that issues such as underfilling can lead to substantial yield loss.
Companies are working on various approaches to further refine TSV processes. Innovations include utilising alternative conductive materials and optimising electron plating methods to fill TSVs more efficiently. The industry is recognising that smaller TSVs might assist in achieving substantial reductions in overall device size while facilitating enhanced performance metrics.
Developments in backside power delivery, particularly for cutting-edge 2nm node devices, show promise in minimizing power losses and improving efficiencies across integrated circuits. Eric Beyne from imec detailed that this approach involves segregating power from signal lines to drive down voltage droop, reflecting a clear trend toward addressing the challenges of modern chip design.
One significant goal in the realm of TSV technology is the emergence of nanoTSVs (nTSVs), which aims to enhance power delivery with designs that allow for effective energy distribution across chip layers. Advanced methodologies involve considerations for the increasingly fine pitch of metal layers, which pose unique challenges in terms of resource routing in backend of line (BEOL) processing.
Various industry players are investing in refining the TSV process to support the ongoing integration of diverse functionalities into a singular chip package. This involves modelling systems at the package level, allowing firms like Amkor to assess and simulate the implications of design alterations before proceeding to physical prototype manufacturing, hence reducing the risk of errors and accelerating development timelines.
As the semiconductor landscape evolves, the welding of through-silicon via technology with emerging applications—such as the integration of photonic ICs, logic and memory elements, and RF systems—illustrates the critical importance of innovative TSV solutions. The industry is likely to witness further progress in creating efficient, high-density vertical interconnections that underpin the next generation of integrated technologies.
Source: Noah Wire Services