A prominent figure in China's endeavour to develop processors based on the RISC-V instruction set architecture has announced plans for the project's delivery in 2025, potentially introducing a design that could compete in the datacentre market. Yungang Bao, associated with the Institute of Computing Technology at the Chinese Academy of Sciences, shared these insights in a recent post on the Chinese social media platform Weibo.
The initiative, known as the Xiangshan project, aims to utilise the permissively licensed RISC-V ISA to create a high-performance chip, with its Scala source code being made publicly available for developers and engineers. Yungang Bao has expressed aspirations similar to those of Red Hat in its contributions to the Linux community, emphasising the importance of open-source principles in fostering innovation and collaboration within the technology sector.
Historically, the Xiangshan project has set targets for semi-annual releases of its designs. The most recent was a second-generation chip named Nanhu, which was completed in late 2023. This silicon operates at 2GHz and was fabricated using a 14nm process node. The project is now transitioning towards a third-generation model, called Kunminghu, which has been revealed through an architectural overview.
The specific capabilities of the 64-bit RISC-V Kunminghu processor remain uncertain; however, the latest project updates indicate simulated testing of a design capable of running at 3GHz. Bao acknowledged that the team has faced challenges in maintaining its projected timeline, attributing the slower pace to the inherent complexities involved in developing advanced chip technology. He remarked on the project’s focused efforts throughout 2024 to continuously optimise area and power consumption metrics for the third-generation design, revealing that they achieved an improvement within 8% of Arm's Neoverse 2 CPU core.
This advancement holds significant implications, given that RISC-V is primarily employed in lower-tier silicon. Elevating this technology to compete on a higher level would represent a notable progression for the architecture. Furthermore, the Xiangshan project operates under the Mulan PSL-2.0 license, which facilitates a royalty-free and globally accessible framework for the reproduction, modification, and distribution of intellectual property. This open-source approach contrasts sharply with the license-based business models of established players like Arm, Intel, and AMD, and mirrors the disruptive path that Linux took to secure a dominant position in the operating systems market.
Another considerable factor underpinning the Xiangshan initiative is China's goal of reducing its dependence on foreign technologies. If successful, the project could produce competitive processors, thereby lessening the impact of sanctions that restrict the sale of cutting-edge chips to China.
While the excitement surrounding Bao's announcement is palpable, it remains to be seen how the Xiangshan project progresses over the coming years. The design of the third-generation chips has yet to debut or be integrated into silicon products, and previous deadlines have already been missed. The path from conceptual design to operational silicon products is notoriously lengthy, compounded by the need to incentivise developers to engage with the new platform. Therefore, as the Xiangshan narrative unfolds, it will be a topic of continued intrigue within the tech industry.
Source: Noah Wire Services