Synopsys and TSMC Collaborate to Propel AI and Multi-Die Semiconductor Design Innovation
Silicon Valley, 10 October 2023 — Synopsys, Inc., a leading provider of electronic design automation (EDA) software, has announced a strengthened partnership with Taiwan Semiconductor Manufacturing Company (TSMC) aimed at delivering advanced EDA and intellectual property (IP) solutions. This collaboration leverages TSMC’s state-of-the-art process technologies and 3DFabric technologies, focusing on expediting innovation in artificial intelligence (AI) and multi-die designs.
The demand for high-performance AI applications has driven the semiconductor industry to continually push the boundaries of technology. In light of this, Synopsys and TSMC are working together to address the future needs of AI chip designs, which are expected to house billions to trillions of transistors. By integrating the AI-driven EDA suite powered by Synopsys.ai™, the partnership aims to enhance both productivity and silicon outcomes. Additionally, the collaboration promises comprehensive support for the transition to more complex 2.5D and 3D multi-die architectures.
To address emerging needs in the semiconductor field, the partnership focuses on enhancing backside routing capabilities within the Synopsys digital design pipeline to support TSMC’s forthcoming A16 process. This advancement is set to improve power distribution and signal routing, ultimately leading to optimal design performance and density. For design teams grappling with increasing physical verification complexities, Synopsys offers Interoperable Process Design Kits (iPDKs) and Synopsys IC Validator™ physical verification runsets tailored for TSMC’s N2 technology.
Further extending their collaborative efforts, Synopsys and TSMC have streamlined the deployment of EDA tools on the cloud through TSMC’s Cloud Certification. This initiative aims to provide joint clients with cloud-compatible EDA tools that guarantee precise results while seamlessly integrating with TSMC’s advanced process technology. Synopsys’ cloud-certified tools encompass various functionalities, including synthesis, placement, routing, static timing and power analysis, transistor-level static timing analysis, custom implementation, circuit simulation, EMIR analysis, and design rule verification.
In partnership with Ansys and TSMC, Synopsys is also addressing complex multi-physics challenges associated with multi-die designs through a comprehensive system analysis workflow. This workflow utilises the Synopsys 3DIC Compiler unified exploration-to-signoff platform, integrating 3DSO.ai and Ansys’s RedHawk-SC™ power integrity signoff platform for both digital and 3D ICs. Certification from TSMC for the 3DIC Compiler platform, combined with TSMC’s 3DFabric technologies (TSMC-SoIC® and CoWoS packaging), supports enhanced thermal and IR-aware timing analysis.
Recognising the importance of reliability in multi-die technology, Synopsys is offering extensive multi-die testing solutions that align with Synopsys UCIe and HBM3 IP standards. These solutions promise the integrity of multi-die packages during manufacturing tests and in-field assessments. In collaboration with TSMC, Synopsys has also developed a test chip using TSMC’s CoWoS interposer technology. This chip includes functionalities for comprehensive testing, monitoring, debugging, and repair.
Synopsys’ Monitoring, Test, and Repair (MTR) IP for UCIe PHY ensures testability at various levels, including the die, die-to-die interface, and multi-die package. This facilitates optimisation during design, production ramp-up, mass production, and field deployment, with capabilities such as predictive maintenance and mission mode signal integrity monitoring.
The long-standing partnership between Synopsys and TSMC continues to produce cutting-edge solutions that meet the evolving demands of the semiconductor industry, paving the way for future advancements in AI and multi-die design technologies.
Source: Noah Wire Services