Synopsys, a leader in semiconductor design and intellectual property, has announced a cutting-edge solution aimed at revolutionising AI data centre chip efficiency. The company's latest offering, the Universal Chiplet Interconnect Express (UCIe) IP solution, promises to address the rising demands of data centres grappling with complex computational workloads, particularly those involving heterogeneous and homogeneous dies.
The new technology, which Synopsys has optimised to operate at speeds of up to 40 Gbps per pin, integrates the UCIe protocol standards 2.0 and 1.1. This protocol is pivotal in facilitating die-to-die communication within a System on a Chip (SoC), especially in sophisticated multi-die configurations, significantly enhancing the flow of data within chip systems.
A standout feature of the UCIe IP solution is its support for flit mode in UCIe 1.1. 'Flit', short for Flow Control Unit, refers to a minimal unit of data transported across interconnect networks. This improvement enables streaming protocols to conveniently map onto existing flit formats used by other interconnect standards such as PCIe and CXL, thereby enhancing data transfer efficiency. The solution supports varied link widths, such as x8 or x4, offering greater flexibility in design and configuration, and is further enhanced by a stack multiplexer that allows multiple protocols to share a single link concurrently.
To handle multi-module configurations effectively, Synopsys has introduced a multi-module link mode, and an Asymmetric Mode feature customises configurations based on data flow direction, offering superior performance over uniform setups.
The architectural framework of the UCIe IP solution comprises three integrated IP components: Controller IP, PHY (Physical Layer) IP, and Verification IP. The Controller IP includes a D2D Adapter and Protocol Layer, facilitating both single and multi-module configurations. The PHY IP maintains the physical layer connectivity between various dies and enhances data throughput using a single reference clock feature, negating the need for more traditional and resource-intensive phase-locked loops.
Synopsys has underscored the importance of the Verification IP, which provides tools and tests aligned with the latest UCIe specifications, ensuring robust die-to-die communication within multi-die packages. It contains pre-built test suites and specification-tied test cases to streamline verification and enhance efficiency across different UCIe design topologies, which include interfaces like the Flit-aware D2D interface and Raw D2D interface.
The PHY IP delivers an impressive 25% increase in bandwidth over existing UCIe specifications, capable of managing data up to a staggering 40 Gbps per pin, culminating in a total bandwidth of 12.9 Tbps/mm. This performance is supported by a mature architecture that maximises efficiency with a 100 MHz single reference clock and low-voltage signalling, crucial for energy savings and reducing silicon usage.
In addition, the solution includes integrated signal integrity monitors for assessing signal quality and maintaining reliability throughout the silicon lifecycle, which is a salient feature for designers ensuring the consistency of multi-die package communications.
Built upon a silicon-proven architecture, the UCIe IP solution has demonstrated interoperability with multiple advanced foundry processes. This not only showcases the robustness of Synopsys's design but also assures potential integration into other systems employing diverse packaging techniques and node technologies like 7nm and 5nm.
This innovative UCIe IP solution signifies a significant leap forward in meeting the demands for efficient interconnect solutions in AI data centres, promising enhanced adaptability, reliability, and system performance.
Source: Noah Wire Services