Arteris Enhances SoC Design with Advanced Network-on-Chip Innovations for Generative AI
Arteris, a leading network-on-chip (NoC) IP company, has announced significant enhancements to its SoC design capabilities, aimed at supporting the burgeoning demands of generative AI products. With the fast-paced evolution of AI technologies, companies are increasingly turning towards optimized SoC configurations to enhance performance and efficiency. To address this need, Arteris has introduced expanded tiling capabilities and extended mesh topology support within its NoC IP solutions.
The advancements include the ability to scale compute performance by over ten times, enabling design teams to align with rigorous project schedules and meet power, performance, and area (PPA) objectives efficiently. This innovation comes in response to the industry's quest to enhance SoC design performance—critical for handling intensive AI and machine learning tasks.
Arteris’ patented network-on-chip IP facilitates the collaboration of cache-coherent and non-coherent interconnects, a feature that forms the backbone of its tiling and mesh topology solutions. These features in Arteris’ flagship products—FlexNoC and Ncore—provide design engineers with the tools to transform chip architectures into modular, scalable units through the replication of 'soft tiles'. These tiles are individual functional units that can be seamlessly integrated, verified, and optimized, significantly reducing design time.
The integration of tiling with mesh topologies offers transformative benefits for the incorporation of AI compute into SoCs. This approach allows for a reduction in auxiliary processing unit (XPU) sub-system design time and overall SoC connectivity execution time by up to 50% compared to manually integrated, non-tiled designs. Arteris highlights that the capability to deactivate groups of NoCs when not required can further reduce power consumption. Additionally, this topology enables dynamic activation of processing elements as per workload requirements, boosting overall power efficiency by 20%.
The first implementation of NoC tiling organizes Network Interface Units (NIUs) into modular blocks, thereby improving scalability, efficiency, and reliability for SoC designs. These improvements cater to increasingly advanced AI computations required for tasks such as Vision processing, Machine Learning models, Deep Learning, Natural Language Processing, and Generative AI applications, including both training and inference, and extending to edge computing scenarios.
Arteris has made its enhanced FlexNoC and Ncore NoC IP products with tiling and extended mesh topology available to early-access customers and partners. This rollout positions Arteris as a pivotal player in facilitating the integration of advanced AI functionalities in SoC designs, offering scalable solutions to meet the complex requirements of contemporary AI workloads.
Source: Noah Wire Services